The present invention relates generally to circuit analysis and partitioning and more specifically, to a signal flow driven circuit analysis and partitioning technique for mixed-signal circuit performance optimization, yield enhancement and layout optimization.
It should be appreciated that circuit analysis and partitioning have been in use for years with digital designs. Typically, circuit analysis and partitioning include the manual partitioning of circuit blocks based on their functionality and physical requirements during the circuit design and layout stages. For radio frequency (RF)/Analog circuit blocks, identifying the critical signal flow is either not performed or implicitly identified at the layout stages manually by layout designers. Circuit optimization is commonly performed by trial-and-error with detailed simulators, such as SPICE.
The main problem with conventional circuit analysis and partitioning is that mixed signal circuit designs often suffer sub-optimal block level partitioning or no partitioning at all due to the lack of an automated solution. This results in either compromised performance of the product or excessive physical area of the layout. Another problem with conventional circuit analysis and partitioning is that massive numerical simulations are needed to optimize the performance of the circuit. Simulation can be so prohibitively time and/or computation power intensive, that performance optimization may not be feasible for a certain scale of circuits. Yet another problem with conventional circuit analysis and partitioning is the difficulty to assure high quality layout, as it is up to the layout designer to manually identify the critical signal path during the layout stage, which is largely dependent on designers' experience level and is susceptible to errors.
In these respects, the signal flow driven circuit analysis and partitioning technique according to the present invention substantially departs from the conventional concepts and designs of the prior art, and in so doing provides an apparatus primarily developed for the purpose of mixed signal circuit performance optimization, yield enhancement and layout optimization.